cpuid.amd

union LeafExt5Information;

L1 Cache and TLB Identifiers.

The associativity fields are encoded as follows:

Specification AMD

CpuInfo info;

ubyte L1ITlb2and4MSize;

Instruction TLB number of entries for 2 MB and 4 MB pages.

ubyte L1ITlb2and4MAssoc;

Instruction TLB associativity for 2 MB and 4 MB pages.

ubyte L1DTlb2and4MSize;

Data TLB number of entries for 2 MB and 4 MB pages.

ubyte L1DTlb2and4MAssoc;

Data TLB associativity for 2 MB and 4 MB pages.

ubyte L1ITlb4KSize;

Instruction TLB number of entries for 4 KB pages.

ubyte L1ITlb4KAssoc;

Instruction TLB associativity for 4 KB pages.

See Also:

CPUID Fn8000_0005_EDX[L1IcAssoc].

ubyte L1DTlb4KSize;

Data TLB number of entries for 4 KB pages.

ubyte L1DTlb4KAssoc;

Data TLB associativity for 4 KB pages.

See Also:

CPUID Fn8000_0005_EDX[L1IcAssoc].

ubyte L1DcLineSize;

L1 data cache line size in bytes.

ubyte L1DcLinesPerTag;

L1 data cache lines per tag.

ubyte L1DcAssoc;

L1 data cache associativity.

See Also:

CPUID Fn8000_0005_EDX[L1IcAssoc].

ubyte L1DcSize;

L1 data cache size in KB.

ubyte L1IcLineSize;

L1 instruction cache line size in bytes.

ubyte L1IcLinesPerTag;

L1 instruction cache lines per tag.

ubyte L1IcAssoc;

L1 instruction cache associativity.

ubyte L1IcSize;

L1 instruction cache size KB.

union LeafExt6Information;

L2/L3 Cache and TLB Identifiers.

This function contains the processor’s second level cache and TLB characteristics for each core. The EDX register contains the processor’s third level cache characteristics that are shared by all cores of the processor.

Note Use decodeL2orL3Assoc. to get final result for any *Assoc field.

Specification AMD

CpuInfo info;

CPUID payload

const pure nothrow @nogc @property @trusted uint L2ITlb4KSize();

L2 instruction TLB number of entries for 4 KB pages.

const pure nothrow @nogc @property @trusted uint L2ITlb4KAssoc();

L2 instruction TLB associativity for 4 KB pages.

const pure nothrow @nogc @property @trusted uint L2DTlb4KSize();

L2 data TLB number of entries for 4 KB pages.

const pure nothrow @nogc @property @trusted uint L2DTlb4KAssoc();

L2 data TLB associativity for 4 KB pages.

const pure nothrow @nogc @property @trusted uint L2ITlb2and4MSize();

L2 instruction TLB number of entries for 2 MB and 4 MB pages. The value returned is for the number of entries available for the 2 MB page size; 4 MB pages require two 2 MB entries, so the number of entries available for the 4 MB page size is one-half the returned value.

const pure nothrow @nogc @property @trusted uint L2ITlb2and4MAssoc();

L2 instruction TLB associativity for 2 MB and 4 MB pages.

const pure nothrow @nogc @property @trusted uint L2DTlb2and4MSize();

L2 data TLB number of entries for 2 MB and 4 MB pages. The value returned is for the number of entries available for the 2 MB page size; 4 MB pages require two 2 MB entries, so the number of entries available for the 4 MB page size is one-half the returned value.

const pure nothrow @nogc @property @trusted uint L2DTlb2and4MAssoc();

L2 data TLB associativity for 2 MB and 4 MB pages.

const pure nothrow @nogc @property @trusted uint L2LineSize();

L2 cache line size in bytes.

const pure nothrow @nogc @property @trusted uint L2LinesPerTag();

L2 cache lines per tag.

const pure nothrow @nogc @property @trusted uint L2Assoc();

L2 cache associativity.

const pure nothrow @nogc @property @trusted uint L2Size();

L2 cache size in KB.

const pure nothrow @nogc @property @trusted uint L3LineSize();

L3 cache line size in bytes.

const pure nothrow @nogc @property @trusted uint L3LinesPerTag();

L3 cache lines per tag.

const pure nothrow @nogc @property @trusted uint L3Assoc();

L3 cache associativity. L3 cache associativity.

const pure nothrow @nogc @property @trusted uint L3Size();

L3 cache size. Specifies the L3 cache size is within the following range: (L3Size * 512KB) <= L3 cache size < ((L3Size+1) * 512KB).

union LeafExt8Information;

Long Mode Address Size Identifiers.

Extended Feature Extensions ID EBX.

Size Identifiers.

Specification AMD

CpuInfo info;

CPUID payload

const pure nothrow @nogc @property @trusted uint L2ITlb4KSize();

Maximum physical byte address size in bits

const pure nothrow @nogc @property @trusted uint PhysAddrSize();

Maximum linear byte address size in bits

const pure nothrow @nogc @property @trusted uint GuestPhysAddrSize();

Maximum guest physical byte address size in bits

const pure nothrow @nogc @property @trusted uint CLZERO();

Clear Zero Instruction

const pure nothrow @nogc @property @trusted uint IRPerf();

Instructions retired count support

const pure nothrow @nogc @property @trusted uint XSaveErPtr();

const pure nothrow @nogc @property @trusted uint NC();

Number of threads in the package - 1

const pure nothrow @nogc @property @trusted uint ApicIdCoreIdSize();

The number of bits in the initial value that indicate thread ID within a package.

const pure nothrow @nogc @property @trusted uint PerfTscSize();

performance time-stamp counter size

union LeafExt1EInformation;

Extended APIC ID.

Core Identifiers.

Node Identifiers.

Specification AMD

CpuInfo info;

CPUID payload

uint ExtendedApicId;

Extended APIC ID

ubyte CoreId;

Core ID

ubyte ThreadsPerCore;

The number of threads per core is ThreadsPerCore+1.

ushort __reserved__EBX;

const pure nothrow @nogc @property @trusted uint NodesPerProcessor();

Node per processor.

const pure nothrow @nogc @property @trusted uint NodeId();

Node ID

pure nothrow @nogc @safe T decodeL2or3Assoc(T = uint)(uint assoc);

Decodes Associativity Fields for L2/L3 Cache or TLB. T.max is used to represent full-associative Cache/TLB.