cpuid.intel

struct Leaf2Information;

TLB and Cache information.

For convinient Cache information see also Leaf4Information..

Specification Intel

Examples:

auto leaf2 = Leaf2Information(_cpuid(2));

Cache il1;

Level-1 instuciton cache

Cache l1;

Level-2 data cache

Cache l2;

Level-2 unified cache

Cache l3;

Level-2 unified cache

Tlb itlb;

Intruction TLB

Tlb hitlb;

Intruction TLB, huge pages

Tlb dtlb;

Data TLB

Tlb hdtlb;

Data TLB, huge pages

Tlb gdtlb;

Data TLB, giant pages

Tlb dtlb1;

Data TLB1

Tlb hdtlb1;

Data TLB1, huge pages

Tlb utlb;

Second-level unified TLB

Tlb hutlb;

Second-level unified TLB, huge pages

Tlb gutlb;

Second-level unified TLB, giant pages

int prefetch;

prefetch line size

int trace;

Cache trace

bool noCacheInfo;

true if CPUID leaf 2 does not report cache descriptor information. use CPUID leaf 4 to query cache parameters.

union Leaf4Information;

Deterministic Cache Parameters for Each Level.

** - Add one to the return value to get the result.

Specification Intel

Examples:

if(maxBasicLeaf >= 4 && vendorIndex == VendorIndex.intel)
{
    Cache cache = void;
    Leaf4Information leaf4 = void;
    foreach(ecx; 0..12)
    {
        leaf4.info = _cpuid(4, ecx);
        if(!leaf4.type)
            break;
        leaf4.fill(cache);
        debug(cpuid) import std.stdio;
        debug(cpuid) writefln("Cache #%s has type '%s' and %s KB size", ecx, leaf4.type, leaf4.size);
    }
}

CpuInfo info;

CPUID payload

enum Type: int;

noMoreCaches

data

instruction

unified

const pure nothrow @nogc @property @trusted Type type();

Cache Type Field.

const pure nothrow @nogc @property @trusted uint level();

Cache Level (starts at 1).

const pure nothrow @nogc @property @trusted bool selfInitializing();

Self Initializing cache level (does not need SW initialization).

const pure nothrow @nogc @property @trusted bool fullyAssociative();

Fully Associative cache.

const pure nothrow @nogc @property @trusted uint maxThreadsPerCache();

Maximum number of addressable IDs for logical processors sharing this cache. **

const pure nothrow @nogc @property @trusted uint maxCorePerCPU();

Maximum number of addressable IDs for processor cores in the physical package **

const pure nothrow @nogc @property @trusted uint l();

System Coherency Line Size **.

const pure nothrow @nogc @property @trusted uint p();

Physical Line partitions **.

const pure nothrow @nogc @property @trusted uint w();

Ways of associativity **.

const uint s;

Number of Sets **.

const pure nothrow @nogc @property @trusted bool invalidate();

Write-Back Invalidate/Invalidate. false if WBINVD/INVD from threads sharing this cache acts upon lower level caches for threads sharing this cache. true if WBINVD/INVD is not guaranteed to act upon lower level caches of non-originating threads sharing this cache.

const pure nothrow @nogc @property @trusted bool inclusive();

true - Cache is not inclusive of lower cache levels. false - Cache is inclusive of lower cache levels.

const pure nothrow @nogc @property @trusted bool complex();

false - Direct mapped cache. true A complex function is used to index the cache, potentially using all address bits.

pure nothrow @nogc @property uint size()();

Compute cache size in KBs.

pure nothrow @nogc @property void fill()(ref Cache cache);